Frequency Range 3 (FR3), spanning 7.125-24.25 GHz, is emerging as a promising spectrum for future 6G wireless systems, offering a balance between the wide coverage of sub-7 GHz FR1 and the high capacity of millimeter-wave FR2. This project develops blocker-tolerant receiver architectures and CMOS integrated circuits for FR3 operation. The research explores the integration of electromagnetic structures with N-path mixers, multi-mode mixer-first receivers, and adaptive receiver architectures that transition between LNA-first and mixer-first operation to extend bandwidth, improve blocker tolerance, reduce noise figure, and enhance energy efficiency. A blocker-tolerant CMOS low-noise receiver is designed for FR3 applications.

Publications

• J. Joy, R. Nikandish, H. Rahmani, and S. Rangan, “Discrete-Time Modeling and Analysis of N-Path Receivers: Interference and Nonlinear Distortion,” Under Review.

• R. Nikandish and H. Rahmani, Balanced Mixer-First Receiver, U.S. Provisional Patent App. No. 63/920,162, Filing Date: April 2026.

• R. Nikandish and H. Rahmani, Interference-Tolerant Receiver with Adaptive LNA-First to Mixer-First Reconfiguration, U.S. Provisional Patent App. No. 63/920,162, Filing Date: November 2025.

Contactless biochemical sensing is an emerging paradigm for next-generation wearable healthcare devices. Unlike conventional invasive approaches, it enables continuous monitoring of physiological biomarkers for early disease detection, health monitoring, and personalized medicine. This project investigates contactless glucose sensing using millimeter-wave scattering and machine learning. A 60-GHz electromagnetic sensor collects signal reflections from in-vitro glucose samples, while convolutional neural networks (CNNs) and transformer models estimate glucose concentration. The proposed end-to-end system achieves over 99% prediction accuracy with a fine resolution of 10 mg/dL using memory-efficient machine learning models. This work demonstrate the potential of combining millimeter-wave sensing with AI for future wearable biomedical devices.

Publications

• R. Nikandish, J. He, C. Sheedy, B. Haghi, R. Crowe and D. Rao, "Contactless Biochemical Sensing with Millimeter-Wave Scattering and Memory-Efficient Deep Learning," Under Review

• R. Nikandish, C. Sheedy, J. He, R. Crowe and D. Rao, "Contactless Glucose Sensing Using Miniature mm-Wave Radar and Tiny Machine Learning," IEEE Journal of Microwaves, March 2025. 

• R. Nikandish, C. Sheedy, and J. He, Non-Invasive Glucose Sensing Systems and Methods, UK Patent Application No. 2417825.3, Filing Date: December 2024.

Deep learning has the potential to extract complex patterns from electrocardiogram (ECG) signals for accurate heartbeat classification. Most existing approaches prioritize classification accuracy, overlooking the stringent memory and computational constraints of wearable medical devices. This project develops a memory-efficient heartbeat classification framework based on multi-feature fusion and bidirectional long short-term memory (Bi-LSTM) neural networks. The proposed models are compressed using post-training quantization techniques, including dynamic range quantization (DRQ) and 8-bit integer (INT8) quantization, significantly reducing memory requirements while maintaining high accuracy. The resulting compact model achieves high classification accuracy with a memory footprint of only 139 kB, enabling practical AI deployment on resource-constrained wearable devices.

Publications

• R. Nikandish, J. He and B. Haghi, "Multi-Feature Fusion and Compressed Bi-LSTM for Memory-Efficient Heartbeat Classification on Wearable Devices," IEEE Journal of Biomedical and Health Informatics, 2026.

Low-power radar system-on-chip (SoC) technologies are enabling emerging applications such as vital-sign monitoring, human-machine interaction, Internet of Things (IoT) sensing, and robotics. The performance of these electromagnetic sensing systems is often limited by circuit imperfections, whose effects remain less understood due to the complexity of nonlinear time-variant (NLTV) circuit behavior. This project develops a comprehensive system-level model to analyze spurs, circuit nonlinearities, and transmitter leakage in frequency-modulated continuous-wave (FMCW) radar systems. The developed model provides valuable insights into the interaction between circuit imperfections and overall radar performance.

Publications

• R. Nikandish, A. Yousefi, and E. Mohammadi, “Spurs in Millimeter-Wave FMCW Radar System-on-Chip,” IEEE Transactions on Radar Systems, Dec. 2023.

• R. Nikandish, A. Yousefi and A. Bozorg, "Impact of Circuit Nonlinearities on the Performance of Millimeter-Wave FMCW Radar-on-Chip Systems," IEEE Radar Conference (RadarConf22), New York City, NY, USA, 2022.

Quantum computing has the potential to revolutionize computationally intensive tasks by exploiting the unique properties of quantum mechanics. However, the practical realization of large-scale fault-tolerant quantum computers remains a long-term challenge due to the limited number and quality of qubits. This project develops a hybrid quantum-classical Generative Adversarial Network (GAN) for near-term noisy intermediate-scale quantum (NISQ) processors. The proposed architecture combines scalable parameterized quantum circuits with classical neural networks to efficiently leverage the strengths of both computing paradigms. Its performance is evaluated using Kullback-Leibler (KL) and Jensen-Shannon (JS) divergence metrics. This work demonstrates the potential of hybrid quantum-classical machine learning.

Publications

• A. O’Dwyer Boyle and R. Nikandish, “A Hybrid Quantum-Classical Generative Adversarial Network for Near-Term Quantum Processors," IEEE Access, July 2024.

Broadband low-noise amplifiers (LNAs) operating in the 20-40 GHz millimeter-wave spectrum are key building blocks for 5G FR2 communications, satellite systems, and automotive radar. Achieving simultaneously high gain, low noise figure, and wide bandwidth remains challenging due to the impact of transistor parasitic capacitances at millimeter-wave frequencies. This project develops innovative broadband LNA architectures based on transformer-feedback techniques to compensate for parasitic capacitance effects and extend bandwidth. The proposed designs include a dual-transformer feedback architecture for inter-stage parasitic capacitance cancellation (IEEE TMTT 2015) and a multi-feedback output stage combined with transistor-width tapering to enhance bandwidth and linearity (IEEE MWCL 2016). These techniques advance the design of broadband millimeter-wave LNAs for wireless connectivity and sensing applications.

Publications

• G. Nikandish, A. Yousefi and M. Kalantari, "A Broadband Multistage LNA With Bandwidth and Linearity Enhancement," IEEE Microwave and Wireless Components Letters, Oct. 2016.

• G. Nikandish and A. Medi, "Transformer-Feedback Interstage Bandwidth Enhancement for MMIC Multistage Amplifiers," IEEE Transactions on Microwave Theory and Techniques, Feb. 2015.

Distributed amplifiers are elegant broadband architectures capable of achieving extremely wide bandwidths for high-frequency integrated circuits. This project develops innovative distributed amplifier architectures to overcome the bandwidth and noise limitations. A transformer-coupled distributed amplifier is proposed and implemented in an integrated circuit process, where distributed transformer coupling compensates the gate-drain capacitance across the entire operating bandwidth (IEEE TMTT 2014). In addition, a tapered distributed low-noise amplifier (LNA) architecture is developed to improve the average noise figure by 1 dB over a 40-GHz bandwidth (IEEE TCAS-II 2018). These architectures advance broadband distributed amplifiers for high-speed wireless communications.

Publications

• G. Nikandish and A. Medi, “A 40-GHz Bandwidth Tapered Distributed LNA,” IEEE Transactions on Circuits and Systems II: Express Briefs, Nov. 2018.

• G. Nikandish and A. Medi, “Unilateralization of MMIC Distributed Amplifiers,” IEEE Transactions on Microwave Theory and Techniques, Dec. 2014.

Power amplifiers (PAs) are among the most critical components of wireless transmitters, and their output power, efficiency, and linearity largely determine the overall performance of communication systems. In 5G transmitters, PAs must efficiently amplify wideband modulated signals with high peak-to-average power ratios (PAPRs). This project develops several innovative PA architectures implemented in GaN integrated circuit technology to enhance efficiency, bandwidth, and linearity. The key contributions include the unbalanced PA architecture for back-off efficiency enhancement (IEEE JSSC 2021), a PA with a minimum-inductance filter matching network (IEEE TCAS-I 2020), and a PA with a multi-resonance wideband harmonic matching network (IEEE TCAS-I 2022). These architectures advance high-efficiency broadband power amplifiers for next-generation wireless communications.

Publications

• R. Nikandish, "GaN Integrated Circuit Power Amplifiers: Developments and Prospects," IEEE Journal of Microwaves, Jan. 2023.

• G. Nikandish, A. Zhu, and R. B. Staszewski, Power Amplifiers, U.S. Patent US 2022/0158594 A1, Publication Date: May 2022.

• G. R. Nikandish, A. Nasri, A. Yousefi, A. Zhu and R. B. Staszewski, "A Broadband Fully Integrated Power Amplifier Using Waveform Shaping Multi-Resonance Harmonic Matching Network," IEEE Transactions on Circuits and Systems I, Regular Papers, Jan. 2022.

• G. R. Nikandish, R. B. Staszewski and A. Zhu, “Unbalanced Power Amplifier: An Architecture for Broadband Back-Off Efficiency Enhancement,” IEEE Journal of Solid-State Circuits, Feb. 2021.

• G. R. Nikandish, R. B. Staszewski and A. Zhu, "A Fully Integrated GaN Dual-Channel Power Amplifier With Crosstalk Suppression for 5G Massive MIMO Transmitters," IEEE Transactions on Circuits and Systems II: Express Briefs, Jan. 2021.

• G. R. Nikandish, R. B. Staszewski, and A. Zhu, “Broadband Fully Integrated GaN Power Amplifier with Minimum-Inductance BPF Matching and Two-Transistor AM-PM Compensation,” IEEE Transactions on Circuits and Systems I, Regular Papers, Dec. 2020.

RF power amplifiers (PAs) often require power-combining networks to achieve high output power. Designing these networks with low insertion loss and wide bandwidth remains a significant challenge. This project develops innovative power-combining and harmonic-termination techniques for high-efficiency multi-watt PAs. The proposed architectures include crossbar and tree power-combining networks for broadband operation (IEEE TMTT 2013). In addition, a harmonic-termination network is proposed to terminate an arbitrary number of harmonics using a minimal number of circuit elements (IEEE TMTT 2014). These techniques advance the design of broadband, high-efficiency RF PAs for future wireless communication systems.

Publications

• G. Nikandish, E. Babakrpur and A. Medi, "A Harmonic Termination Technique for Single- and Multi-Band High-Efficiency Class-F MMIC Power Amplifiers," IEEE Transactions on Microwave Theory and Techniques, May 2014.

• G. Nikandish and A. Medi, "A Design Procedure for High-Efficiency and Compact-Size 5–10-W MMIC Power Amplifiers in GaAs pHEMT Technology," IEEE Transactions on Microwave Theory and Techniques, Aug. 2013.

Pipeline analog-to-digital converters (ADCs) achieve high resolution and high sampling rates by successively extracting digital bits using cascaded pipeline stages with low-resolution sub-ADCs. Their architecture is inherently tolerant to comparator offsets through digital error correction based on inter-stage bit redundancy. In this project, a comprehensive system-level model is developed for the impact of circuit imperfections on ADC performance metrics, including integral nonlinearity (INL) and signal-to-noise-and-distortion ratio (SNDR). The model accounts for sampling noise, circuit nonlinearities, random capacitor mismatch, and the finite gain of operational amplifiers. Power consumption is minimized through stage-by-stage scaling of sampling capacitors and amplifier gain. A CMOS pipeline ADC is designed using a 2.5-bit first stage followed by multiple 1.5-bit stages. The design incorporates clock-bootstrapped switches, gain-boosted operational amplifiers providing more than 100 dB DC gain, and low-power latched comparators to achieve high accuracy and energy efficiency.

Publications

• G. Nikandish, Design of High-Resolution High-Speed Pipeline Analog-to-Digital Converters, M.Sc. Thesis, Sharif University of Technology. 

• G. Nikandish, B. Sedighi and M. Sharif Bakhtiar, "INL Prediction Method in Pipeline ADCs," IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Singapore.

• G. Nikandish, B. Sedighi and M. Sharif Bakhtiar, "Performance Comparison of Switched-Capacitor and Switched-Current Pipeline ADCs," IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, USA.